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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
1.0 General Description
This data sheet covers the AMIS-710616-AS (PI616MC-AS) specification. CIS stands for contact image sensor. It is a one-dimension array of photosensitive elements, designed to image documents with a oneto-one magnification ratio. The sensors are sequentially cascaded to form a one dimensional variable-length line array in multiple integral numbers, hence providing the users with desired lengths. The AMIS-710616-AS is one of these special length line-image arrays. It is configured with a total of eight sub-sections, each section containing a sequential line of five array sensors, with its individual video output line. These eight video outputs are also referred to as tapped outputs. They are all read out in parallel (see Figure 1). The eight sub-sections are sequentially cascaded to form the onedimensional array. It is fabricated on two printed circuit boards (PCB) referred to as sensor boards. Each sensor board contains four sub-sections. The two sensor boards are cascaded in series to form a complete line image sensor of eight sub-sections with a total read length of 325mm. Accordingly, each sensor board contains 20 each of AMIS-720639 (PI3039) image sensors, also a product of AMIS. Hence, for both boards there are a total of eight parallel tapped outputs and 40 each of the AMIS-720639 image array sensors. Each chip has 192 photo sensing cells, hence on one board there are 3840 cell sites and a total of 7680 cell sites for both boards. Each cell site is a photo-detector, which possesses its own independent processing circuit. An associated on-chip digital shift register scans and reads the video signal of each photo detector onto a common output video line. In sections of five sensors, these common output video lines are individually brought out to the I/O connectors of the sensor boards. There are two connectors, one on each board, each containing four video outputs. These connectors are connected via a cable to their respective amplifier boards (see Figure 2). The schematic of the AMIS-710616-AS and its PCB mechanical outline drawing are attached to this data sheet.
2.0 Overview
The AMIS-710616-AS has 324.2mm read width. Its recommended line rate is 192s/line at a 5.0MHz clock rate, but its minimum can be as low as 160s/line at its maximum clocking speed of 6.0MHz. Its sensor photo-site density is 23.25elements/mm. See AMI Semiconductor's AMIS-720639 data sheet, which covers the specifications on the imaging array sensor. Operationally, it requires only the power supplies, +5V and -5V and two input clocks, one is the clock (CP), to operate the internal shift registers and the second is the start pulse (SP), to initiate the output scan.
3.0 Scan Outline
Table 3-1: Scanning Outline Item Readable width Sensor photo-site density Number of total active sensor photo-sites Number of photo-sites per tap Total line read time = read time per section Clock frequency
Specification 324.2mm 23.25elements/mm 7680 elements 960 192s/line 160s/line 5.0MHz 6.0MHz
Note
Typical, tested @ 5.0MHz Clock Minimum, tested @ 6.0MHz Clock Typical Maximum
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
4.0 Physical Outline
Table 4-1: Physical Outline Item Image sensors PCB stiffner board Sensor PCB Data output Sensor board connectors Amplifier PCB board Amplifier board's four connectors
Specification AMIS-720639 PCB stiffner board size 355.6mm x 41.3mm x 6.35mm Size 165.1mm x 21.4mm x 1.62mm Eight analog video outputs Two I/O connectors MOLEX 52610-1590 Size 291.3mm x 76.2mm x 1.6mm Two inputs: MOLEX 52207-1950 Two outputs: ERNI-594083
Note See referenced image sensor data sheet
Two PCBs mounted on the stiffner Used to connect to their respective output amplifiers Mounted are eight output amplifiers for each of the video lines from the sensor boards
5.0 Recommended Operating Conditions (25C)
Table 5-1: Recommended Operating Conditions at 25 C Item Symbol Power supply VDD IDD VSS ISS (1) Video output levels Vpavg (2) Video saturation output VSATA (2) Video line saturation output VSATV Input voltage at digital high (input clocks, SP and CP) VIH Input voltage at digital low (input clocks SP and CP) VIL (3) Clock frequency Freq (4) Clock pulse high duty cycle Duty (3)(5) Clock high duration TPW Integration time Tint Operating temperature
Notes: (1)
Min. 4.5 135
VDD-1.0 0 25 83.3 192s/line 160s/line
Typ. 5.0 150 |-5.0| 45 3.0 5.5 1.2 VDD-.5 5.0 100
Max. 5.5 165 |-5.5| 60
VDD+0.3 0.8 6.0 75
Top
(6)
25
50
Units V ma V ma V V V V V MHz % Ns, at 50 percent duty Typical, tested @ 5.0MHz clock Minimum, tested @ 6.0MHz clock C
(2)
(3)
(4)
(5)
(6)
Vpavg is a symbol representing the average value of every pixel in the complete line scan. Vp(n) is the pixel amplitude of the nth pixel in a line scan. This measurement is taken with the image array under a uniform light exposure. The typical output is specified with a uniform input light exposure of 0.5J/cm2 from a blue Led light source. Two saturated video output levels are specified. One is at the video signal's output amplifier, VSATA, and the other is at the input of the amplifier. In almost all applications, because the integration time is usually too short, there is not enough exposure time to saturate the array sensors. Accordingly, each output amplifier is fixed with a gain of 4.5. Freq is generally fixed for any application for the following reasons: One is the exposure time. With a given light power, the exposure time of the sensor can be related to the clock frequency. The second is the shape of the video output pulse. Because the output video is in pulse charge packets, the signals are processed on the output video line of the sensors. Hence, the signal shape depends greatly upon the amplifier configurations. Please refer to the referenced AMIS-720639 data sheet. It has some brief outline application notes. Under Note 6 on Page 6, there is a discussion about video pulse shapes. On Page 8, 9 and 10 there are discussions on the three types of signal output stages. Duty is the ratio of the clock's pulse width over its pulse period. Because the video pixel output resets during the clock pulse's high period and because the reset requires a finite resetting time, it is recommended to operate the clock duty cycle within the following limits. See the referenced data sheet in Note 3, above. Noting that the larger the duty, the less the signal amplitude, while too short of a clock pulse will not provide enough video reset time and leaves residual charges, the recommended duty is 25 percent for frequencies less than 5MHz and 50 percent for frequencies greater than 5MHz. Tint is determined by the time interval between two start pulses, (SP). Hence, if the SP is generated from a clock count down circuit, it will be directly proportional to the clock frequency and it will be synchronous with the clock frequency. The longest integration time is determined by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion and determine the desired tolerance level for the given system. Top is a conservative engineering estimate. It is based on measurements of similar CIS modules and simple bench top tests, using heat guns and freeze sprays. These will be re-measured during the pilot production under the standard QA practices that are under the control of ISO 9000.
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
6.0 Electro-Optical Characteristics (25C)
Table 6-1: Electro-Optical Characteristics at 25 C Parameter Number of active photo detectors Pixel-to-pixel spacing Line scanning rate
Symbol
Parameter 7680 43.25 192
Units Elements m s/line
Note
Tint
(1)
Clock frequency Red responsivity Green responsivity Blue responsivity Bright output voltage Bright output non-uniformity Adjacent pixel non-uniformity Bright output Non-uniformity total Dark non-uniformity Dark video offset Random noise Modulation transfer function
Freq
(2)
6.0 70 55 35 3.0 <7 <10 <10 <25 -2.0 <11.8 <3.0 >70
MHz V/J/cm2 V/J/cm2 V/J/cm2 V % % % mV Volts p-p mV rms mV %
ExpR
(3)
ExpG ExpB
(3)
(3) (4)
Vpavg
Up (5) Uadj
(6)
@ 5.0MHz clock frequency (see Note 1) Maximum clock frequency (see Note 2) See Note 3 for definition See Note 3 for definition See Note 3 for definition Green light Depends on optical system (see Note 5) Depends on the optical system (see Note 5)
Uptotal Ud (9) Vd RNL MTF
(8)
(7)
(10)
(11)
Sensor only (see Note 11)
Notes: Since this is a prototype module, the following Notes 4, 5, 6, 7, and 8, are on data based on engineering scope measurements. The data will be re-measured during pilot production using all the standard QA practices under the control of ISO 9000 regulations. Furthermore, they will be taken on fully computerized test systems. If required, these prototype data may be revised. Tint is the line-scan rate or integration time. It is determined by the time interval between two SPs. If the SP is generated from a clock count down circuit, it will be directly proportional to clock frequency and it will be synchronous with the clock frequency. The longest integration time is determined by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion to determine the desired tolerance level for the given system. (2) Freq is the clock frequency, which is also equal to the signal data rate. It is generally fixed for many applications for following reasons: One is the exposure time. With a given light power, the exposure time of the sensor depends on the integration time and in most applications it uses clock count down circuits to generate the SP, shift register start pulse. The second is the shape of the video output pulse. Because the output is in pulse packets of video charges, the signals are processed on the output video line of the sensors. The signal shape depends greatly upon the amplifier configurations. Please refer to the referenced AMIS-720639 data sheet. It has some brief outline application notes. Under Note 6 on Page 6, there is a discussion on video pulse shapes. On Page 8, 9 and 10 there are discussions on the three types of signal output stages. (3) The responsivity is the ratio of video signal in volts, divided by the unit exposure (V/micro-Joules/cm 2). This exposure was measured with the output level adjusted to 1.27V. The spread of the measured exposure R-RSP, G-RSP and B-RSP can be used to compute the user's desired signal voltage level. (4) Vpmax = maximum pixel value of Vp(n); Vpmin = minimum pixel value of Vp(n); Vpavg = Vp(n)/7680; where Vp(n) is the nth pixel in a line scan with the module scanning a uniform white target. Vp values are measured with a uniform exposure. (5) Bright output Non-uniformity: Up(+) = [(Vpmax - Vpavg) / Vpavg] x 100% or Up(-)= [(Vpavg - Vpmin) / Vpavg] x 100%, whichever polarity with the highest value is selected. Two further notes: One is that the AMIS-710616-AS has no requirement for an optical system, or a light system. The second is that the nonuniformity is dominated by the LED light bar's non-uniformity so only the sensor non-uniformity is specified. The normal standard CIS modules are enclosed in a self-contained module with a complete optical and LED lighting system. So the light system, usually the LED bar, is included in making the measurement of the optical characteristics. This fixes the optical geometry for the module and the light source. The module's optical characteristics are simply measured with the module placed on a uniform reflecting target with a known reflection density. However, the AMIS-710616-AS is not enclosed with its optical and light source system. Therefore, Up is measured with uniform light source, which directly illuminates the image sensors' photosite. (6) Adjacent Pixel Non-uniformity: Upadj = MAX[ | (Vp(n) - Vp(n+l) | / Vp(n)] x 100%. Upadj is non-uniformity in percentage of Vpavg. It is the maximum difference amplitude between two neighboring pixels. (7) Bright output total non-uniformity: Uptotal = [Vpmax -Vpmin]/Vpavg (8) Dark non-uniformity: Ud = Vdmax - Vdmin: It is measured over the full length of the array with the light source off and the sensors placed in the dark. Vdmax is the maximum pixel value of the video pixel with the exposure off. Vdmin is the minimum pixel value of the video pixel with the exposure off. The references for these levels are the dark level, VDL. (9) Dark output voltage, VDL is the level between the out video pixel dark level and the ground. (10) Random noise, RNL, is measured using two methods; one is to take the measurement tangentially on the scope. This measures an approximate peak-to-peak, p-p, random thermal noise. The other method is in terms of rms. It is estimated by using Gaussian statistical methods. One pixel is selected out of a line scan and its peak values are recorded for multiple line scans. These random peak values are used to estimate the rms values. (1)
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
(11) Modulation transfer function depends on the optical system. Since this system relies on the users optical system, it was not measured. Referring back to Note 5, measurements on Up, all notes that reference the optical measurements apply to MTF measurements as well. Using a conservative engineering estimate, the sensor's MTF is in excess of 70 percent at the optical Nyquest frequency.
7.0 Electrical Timing Characteristics
7.1 Clock Amplitude and Duty Characteristics
Table 7-1: Clock Amplitude and Duty Characteristics Item Clock input voltage Clock input current Clock frequency Line read time Clock pulse duty cycle
Notes: (1) (2) (3) These CP and SP values are compatible with CMOS 74HCXX series logic devices. Freq is not only the clock frequency, but is also equal to the pixel sample rate. See not 2 under Table 6.1. Tint is the line scan read time, which depends on the interval between the SP entries. See Note 1 under Table 6.1. The longest integration time is determined by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion to determine the desired tolerance level for the given system. The definition for the symbols used in the ratio is defined in Section 7.2.
(Ta =25 C) Min. Specification Typ. See Note (1) for values See Note (1) for values 0.100 160 5.0 192 50 6.0 1000 75 MHz s % Max. Units
Symbol VIH (1) VIL (1) IIH (1) IIL (2) Freq Tint
(3) (1)
Condition For values see the notes
Ratio = tw/ to
(4)
25
(4)
7.2 Clock Timing Characteristics This table defines the symbols used in the timing diagram (Figure 3). It is for a single video section, however it applies to all eight video sections. Accordingly, the system-timing diagram is a composition of this timing diagram repeated eight times, with all waveforms in parallel, so electrically the system produces pixels from all eight video sections simultaneously.
Table 7-2: Clock Timing Characteristics Item (2) Clock cycle time (2) Clock pulse width (2) Clock duty cycle Prohibit crossing time of SP Data setup time Data hold time Signal delay time Signal sample time Signal fall time Recommended SP generation
Notes: (1) (2) (3) (4)
Symbol to tw duty tprh tds tdh tdl (3) tsmp tsigf (4) Tonoff
Min. 0.1666 25 30 30 25 125
Typ. 0.200 0.100 50
Max. 10 75
75 75
Units s ns % ns ns ns ns ns ns
This applies to the whole chart. All of the symbol definitions in Table 7-2 are used in Figure 3. For the complete system, there are only two clocks, CP and SP and their logic levels are compatible with CMOS 74HCXX series logic devices. See the notes on clock periods (the inverse of freq) and their duty cycles under Table 5-1 Notes 3 and 4. See AMIS-720639 data sheet Page 6, Table 6A, Note 6. This is the recommended method for SP generation because the shift register loads only on the falling edge.
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
8.0 Maximum Ratings
Table 8-1: Maximum Ratings (Not to be Used for Continuous Operation) Item Symbol DC supply voltage VDD Input voltage (1) Ambient temperature Ambient humidity (1) Maximum operating case temperature
Note: (1) All the referenced parameters are conservative engineering estimates based on a few of the prototypes' PCB. They are based on measurements of similar CIS modules and/or simple bench top tests using heat guns and freeze sprays. However, these parameters will be re-measured during the pilot production using standard QA practices, which are under the control of ISO 9000 regulations.
(1)
Specification 7V 0 to VDD +0.3 0 to 70 C (see note below) -10 to +75 C (see note below) 0 to 80% (see note below) 70 C (see note below)
Note
VIN TA (PCB surface) HA PCB temperature
SP & CP Operational storage Non-condensing
9.0 I/O Connector Pin Configuration
There are two I/0 connectors on the stiffener plate with the two sensor boards. They are MOLEX 52610-1590. They serve to connect the sensor boards to the amplifier boards (see the outline drawing of the system, Figure 2). Two 15 conductor strip lines serve as the interfacing harness. It is depicted with harnesses coming from under the stiffener plate, crossing to the top of the amplifier board and connecting to the two input connectors MOLEX 52207-1950. The final connectors are the two ERNI-594083s. They are the system I/Os. Only one of the two connectors on the stiffener board is specified because both connectors have identical pin-out definitions. There are eight video taps, four from each sensor board and they are sequential re-numbered. The first sensor board video outputs are, 1, 2, 3 and 4. The second sensor board's videos are 5, 6, 7 and 8. 9.1 Two MOLEX 52610-I590 and its Mate to Amplifier Boards MOLEX 52207-1590
Table 9-1: Sensor Board Connectors and Input Connectors for Amplifier Board Pin-outs Pin Numbers Pin Names Symbols I/0 Names and Functions 1 Clock pulse CP I 2 Start pulse SP I 3 Ground GRD I Ground; 0V 4 Power supply VDD I Positive power supply 5 Ground GRD I Ground; 0V 6 Ground GRD I Ground; 0V 7 Ground GRD I Ground; 0V 8 Video output VSEC1 O Tapped 1 video output, Section 1 on Board 1; it is Section 5 on Board 2 9 Analog Ground AGRD I Analog video return line, ground; 0V 10 Video output VSEC2 O Tapped 2 video output, Section 2 on Board 1; it is Section 6 on Board 2 11 Analog Ground AGRD I Analog video return line, ground; 0V 12 Video output VSEC3 O Tapped 3 video output, Section 3 on Board 1; it is Section 7 on Board 2 13 Analog Ground AGRD I Analog video return line, ground; 0V 14 Video output VSEC4 O Tapped 4 video output, Section 4 on Board 1; it is Section 8 on Board 2 5 Analog Ground AGRD I Analog video return line, ground; 0V
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AMIS-710616-AS: CIS PCB
Product Specification
9.2 Amplifier Board Output Connectors, ERNI594083
Data Sheet
There are four connectors on the amplifier board. Two are inputs, which are described above, and two are outputs, which are described below. There is only one table shown for both connectors. They are both identical in their connections except that one is for the outputs of Sensor Board 1 and the other is for the outputs of Sensor Board 2. Accordingly, each of the video outputs after amplification for both sensor boards are labeled, VOUT1, VOUT2, VOUT3 and VOUT4. Videos from Sensor Board 1, VSEC1's corresponding output is VOUT1, VSEC2's corresponding output is VOUT2, VSEC3's corresponding output is VOUT3 and VSEC4's corresponding output is VOUT4. Then the videos from Sensor Board 2 will have their corresponding outputs on the second connector VOUT1, VOUT2, VOUT3 and VOUT4, except their outputs VOUT5, VOUT6, VOUT7 and VOUT8 because those video signals originate from Section 5, Section 6, Section 7 and Section 8 of Sensor Board 2.
Table 9-2: Amplifier Board Output Connectors, ERNI-594083 Pin Numbers Description Row A 1 VDD 2 VDD 3 No connect 4 Ground 5 SP 6 No connect 7 No connect 8 No connect 9 CLK 10 GND 11 No connect 12 No connect 13 No connect 14 GND 15 No connect 16 VSS Description Row B VDD VDD No connect Ground GND GND GND GND GND GND GND GND GND GND No connect VSS Description Row C AGND VOUT1 AGND AGND AGND VOUT2 AGND AGND AGND VOUT3 AGND AGND AGND VOUT4 AGND AGND
Note: The functional description for the symbols used in Table 9-2 are the same as described for the input connector. The two new symbols VSS and CLK are as follows: VSS is negative supply input. CLK is CP.
The locations of Pin 1 on all the connectors are facing the same end (see Figure 2).
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
10.0 Block Diagrams - Figures 1, 2 and 3
Figure 1: Simplified Circuit Block Diagram
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
Figure 2: System Configuration Block Diagram
Figure 3: Timing Diagram
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
11.0 Schematic Diagram
Two reference schematic diagrams are attached to this document (Figure 4 and Figure 5). Only one schematic, CKT 1, Schematic (Figure 1), is required to represent both the Sensor Board 1 and 2 because the circuits are identical. The second one is for the amplifier board and it contains all eight of the amplifiers on one schematic. The circuit description of its structure and operation has been briefly discussed in Section 1 of this document. Its operation follows from the discussion of the simplified block diagram. There are only two input control clocks for the circuits, CP and SP. SP starts the shift register scanning while CP clocks the register and produces the video pixels at its same rate. The clocks are entered through the I/O connectors on both sensor boards. They are both externally buffered with the 74HC00 hexes and applied to the inputs of the image sensors. On each of the two-image array sensor boards there are four sequential video sections. Each video section contains a row of five sequential image array sensors, AMIS-720639. These are all clocks in parallel with CP. The four sections on both boards are clocked with SP in parallel, to initiate all eight video sections and simultaneously begin the eight sequential readouts. All eight lines, four in each sensor board, have reset switches, BU4S66, which parallel resets the video pixel charges after they are readout. These pixels, read out in parallel, are applied to their respective output amplifiers on the amplifier board. The second schematic, CKT 2, Amplifier Board Schematic (Figure 5), is the amplifier board. There are eight amplifiers for processing the output videos from both sensor boards. The amplifier board receives the inputs from the sensor board output connector, J1, through two harnesses. They are connected into the input I/O connectors, J1 and J2, of the amplifier board. Since there are two sensor boards using the same schematic representation, the connector on Sensor Board 1, J1, becomes J2 for the second board. They are physically differentiated and marked as J1 and J2 on the stiffener board. Since all eight sections process their video signals through identical amplifiers, only one amplifier circuit is discussed. The AD8051 is an operational amplifier, which is configured into a non-inverting buffer amplifier with a gain of 4.5. It is used to isolate the video line from its external circuits. The isolated video line then serves as a storage capacitance for the pixels outputs. The pixel charges are read out onto the video line capacitance and integrated. This integrated pixel charge, converted to a voltage pulse, is amplified and produced at the output I/O. The reset switch on the video line, which is located on the sensor board schematic, resets the pixel signal charge prior to the readout of following pixel.
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AMIS-710616-AS: CIS PCB
Product Specification
11.1 Schematic Drawings; CKT 1 and CKT 2
Data Sheet
Figure 4: CKT 1 - Sensor Board Schematic
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
Figure 5: CKT 2 - Amplifier Board Schematic
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
12.0 Drawing on Mechanical Structure
Attached are six mechanical drawings. The first drawing (Figure 6) shows an outline drawing of the complete CIS system, consisting of the stiffener plate, the interconnecting harness and the amplifier board. There are two connector pin configuration tables, one is for the two sensor boards and the input for the amplifier board and the other is for the two output connectors on the amplifier boards. These two tables show the pin numbering and names for the six connectors that are seen in the drawing. For detailed descriptions of the interconnections and their functions, see section 9.0. The second drawing (Figure 7) shows the view of the stiffener board. The stiffener board is a 1/4" aluminum backing plate on which the two image sensor boards are mounted. The schematic drawing provides the dimensions of the plate, its access holes for the twosensor board's connectors, along with all of the required dimensions. The third drawing (Figure 8) shows a view of the two sensor boards mounted on the stiffener board. It shows the direction of the scan, its first pixel location and its video read line location. It provides the dimensions on the connector height, the thickness of PCB board and its component height. The fourth drawing (Figure 9), is a backside view of the stiffener plate. It shows the location of the connectors and its pin order and direction. The fifth drawing (Figure 10) shows a view of the PCB outline. The three views of the board provide the outline dimensions, its length, its width and its thickness. It also depicts the mounting holes and their dimensions and locations. The six drawing (Figure 11), shows a view of the PCB with its connectors.
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Product Specification
AMIS-710616-AS: CIS PCB
12.1 Mechanical Drawings; Drawing 1, 2, 3, 4, 5 and 6
www.amis.com
Molex~52610-1590
Scan Direction Scan Direction
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Molex~52610-1590 Molex~52207-1590 Pin signal assignments : Pin signal assignments : Pin Description Pin Description Molex~52207-1590 ERNI~594083 ERNI~594083 Pin signal assignments : PIC version Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK SP GND VDD GND GND GND VSEC1 Agnd VSEC2 Agnd VSEC3 Agnd VSEC4 Agnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK SP GND VDD GND GND GND VSEC1 Agnd VSEC2 Agnd VSEC3 Agnd VSEC4 Agnd NOTE: 1. No component may excede 5.08mm (0.200inch) from ether side of the board. 2. The ERNI~594083 connectors are exempt from this height limit. 3. 3.175mm (0.125inch) clearance around 6 mounting holes. 4. Dimensions are in millimeter.
Figure 6: Drawing 1 -Top Assemble Outline
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Row A VDD VDD No connect GND SP No connect No connect No connect CLK GND No connect No connect No connect GND No connect VSS Description Row B VDD VDD No connect GND GND GND GND GND GND GND GND GND GND GND No connect VSS Description Row C Agnd Vout 1 Agnd Agnd Agnd Vout 2 Agnd Agnd Agnd Vout 3 Agnd Agnd Agnd Vout 4 Agnd Agnd
PI616MC-AS
A1 Ingrid Chang Ingrid Chang 27-Nov-02
1
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27-Nov-02
Data Sheet
AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
Figure 7: Drawing 2 - Stiffner Plate
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2
6
Product Specification
AMIS-710616-AS: CIS PCB
www.amis.com
Scan Direction Sensor Board 1 Sensor Board 2 Scan Direction Reading Line Specification : (1) A1=5.000.2mm & A2=5.000.2mm. (2) | A1-A2 | = 0.4mm. (3) Both (1) & (2) use the stiffner plate edge as the reference. See SIDE VIEW A. Pin 1 Pin 15 (Components Height) Bottom Layer (Connector side)
3 6
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See SIDE VIEW B.
Figure 8: Drawing 3 - Two Sensor Board
15
Top Layer (Sensor chip and components side)
(Connector Height)
Data Sheet
AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
(Pin 1 Location)
Sensor Board 1 at the back side
Scan Direction
Scan Direction
Sensor Board 2 at the back side
Figure 9: Drawing 4 - Connectors on Stiffner
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Scan Direction
Scan Direction
(Pin 1 Location)
4
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
(PCB Thickness)
Figure 10: Drawing 5 - Amplifier Board
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(PCB Thickness)
5
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
(ERNI~Connector Height)
(PCB Thickness)
Figure 11: Drawing 6 - Amplifier Board with Connectors
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(PCB Thickness)
6
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AMIS-710616-AS: CIS PCB
Product Specification
Data Sheet
13.0 Company or Product Inquiries
For more information about AMI Semiconductor, our technology and our product, visit our Web site at: http://www.amis.com North America Tel: +1.208.233.4690 Fax: +1.208.234.6795 Europe Tel: +32 (0) 55.33.22.11 Fax: +32 (0) 55.31.81.12
Production Technical Data - The information contained in this document applies to a product in production. AMI Semiconductor and its subsidiaries ("AMIS") have made every effort to ensure that the information is accurate and reliable. However, the characteristics and specifications of the product are subject to change without notice and the information is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify that data being relied on is the most current and complete. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. Products sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no other warranty, express or implied, and disclaims the warranties of noninfringement, merchantability, or fitness for a particular purpose. AMI Semiconductor's products are intended for use in ordinary commercial applications. These products are not designed, authorized, or warranted to be suitable for use in life-support systems or other critical applications where malfunction may cause personal injury. Inclusion of AMIS products in such applications is understood to be fully at the customer's risk. Applications requiring extended temperature range, operation in unusual environmental conditions, or high reliability, such as military or medical life-support, are specifically not recommended without additional processing by AMIS for such applications. Copyright (c) 2006 AMI Semiconductor, Inc.
AMI Semiconductor - July 06, M-20595-001 www.amis.com
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